Rod graduated with a Bachelor of Engineering (Computer Systems, Hons I) from the University of Queensland in 1988, and was awarded the University Medal for Academic Excellence.
He joined Austek Microsystems (Adelaide, Australia) in January 1989 as a VLSI Design Engineer, and was responsible for the implementation (using VHDL synthesis to standard cells and full-custom design) of macrocells for an 80386-based write-through cache controller and an 80386-based integrated memory controller.
In addition to his VLSI design work at Austek, Rod also developed and maintained CAD tools for the conversion of logical equations to other formats (including VHDL), a high-level language front-end to analogue simulators (including PSPICE, HSPICE, and an in-house switch-level simulator), and other X Window tools for ASIC design productivity enhancement.
In January 1991, Rod took up an 8 month posting with Austek’s Santa Clara office in California, where he developed a bus-functional VHDL behavioural model of the i486 microprocessor, and a VHDL verification framework for a full-system simulation of an EISA system.
After returning to Adelaide in September 1991, Rod was responsible for the implementation of macrocells for an i486-based write-back cache controller. Austek’s Santa Clara office closed down the Adelaide office in April 1992.
Rod joined Canon Information Systems Research Australia (Sydney, Australia) in June 1992 as an ASIC Design Engineer, and was responsible for the algorithmic research, behavioural VHDL modelling and gate-array implementation of the line dispatcher subsystem of a high-speed image processing system enabling plug-and-play connection of a low refresh rate ferroelectric liquid crystal display (FLCD) to normal workstation CRT outputs. Rod’s work on this system has been patented in the USA (US5576731), Europe (EP0608056, EP0608053), Japan (JP7005860, JP7092947) and Australia (AU672648, AU673556).
As part of the board-level testing of the image processing system, Rod developed software tools to support functional testing of the fabricated chips in the production system, including a Tcl/Tk interface to the on-board monitor (allowing real-time on-screen modification of the partial update registers controlling the display algorithms), and tools to supply input vectors through an in-house high-speed pattern generator and acquire results from a HP logic analyser.
In addition to his ASIC design work at Canon, Rod also developed methodologies and process flow support tools for ASIC design and cross-verification of behavioural VHDL and gate-level schematic models, and continued his work on tools for ASIC design productivity enhancement.
After completing the FLCD project at Canon, Rod joined the Motorola Australia Software Centre (Adelaide, Australia) as a founding member in December 1994. Since then, Rod has led a number of varied projects in areas such as SoC Design, Modelling & Simulation, and development of Computer Aided Design Tools. Rod was instrumental in founding and continuing to develop a world-class SoC design capability for Motorola in Australia.
In July 2004, Motorola spun off its semiconductor design and manufacturing operations to form Freescale Semiconductor. The Adelaide-based SoC design centre became the core of Freescale Semiconductor’s operation in Australia. Rod held the positions of Chief Engineer and Chief SoC Architect at Freescale’s Australia SoC Technology Centre, architecting the most complex SoC networking devices in the Southern Hemisphere - including the MPC8568E PowerQUICC III integrated communications processor.
When Freescale closed it’s Adelaide office in March 2006, Rod joined up with four of his management colleagues from Freescale to form a new company focusing on consulting in the SoC design and embedded software development industry. The Australian Semiconductor Technology Company (ASTC) employs over 30 people and consults to Freescale and other customers world-wide.